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INTEGRATED CIRCUITS
DATA SHEET
SAB9075H Picture-in-Picture (PIP) controller for NTSC
Preliminary specification File under Integrated Circuits, IC02 February 1995
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
FEATURES Display * One or two live pictures can be displayed simultaneously * Wide range of multi-Picture-In-Picture (PIP) modes available * Six 6-bit Analog-to-Digital Converters (ADC) with clamping circuit * Enhanced vertical resolution at most modes for live pictures * Two Phase-Locked-Loops (PLL) with Voltage Controlled Oscillator (VCO) to generate the line-locked clocks * Three 7-bit Digital-to-Analog Converters (DAC) * 4 : 1 : 1 data format * Data reduction factors 1 to 4, 1 to 9 and 1 to 16. I2C-bus programmable * Different single, double and multi-PIP modes can be set * Several aspect ratios can be handled * Reduction factors can be set automatically and manually * Selection of vertical filtering type * Freeze of live pictures * Single-PIP display position, four corners on-screen * Multi-PIP display position, left or right on-screen * Fine tuned display position, H (6-bit), V (6-bit) * Fine tuned acquisition area, H (4-bit), V (4-bit) * Channel-border and live PIP selectable * Eight main-border, sub-border, channel-border and background colours selectable * Border and background brightness adjustable, 30%, 50%, 70% and 100% IRE * Several types of decoder input signals can be set * 6-bit HUE and SAT signals (0 to 5 V) adjustable by I2C-bus * Main and sub-audio mute controllable by I2C-bus. GENERAL DESCRIPTION
SAB9075H
The SAB9075H is a picture-in-picture controller for the NTSC environment in combination with the Integrated NTSC decoder and sync processor TDA8315. The device inserts one or two live video channels with reduced sizes into a live video signal. All video signals are expected to be analog baseband signals. The conversion into the digital environment and back to the analog environment is carried out on-chip. Internal clocks are generated by two PLLs. Due to the two PIP channels and a large external memory, a wide range of PIP modes are offered. The emphasis is put on double-PIP and multi-PIP modes. In combination with the different border colours and some external software the IC concept can be used as an excellent channel selection tool. Some of the I2C-bus registers are for controlling the saturation and HUE of the colours. There are also outputs for the mute function of main and sub-channel.
February 1995
2
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION
SAB9075H
VERSION SOT317-2
SAB9075H QFP100(1) plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm Note
1. When using IR reflow soldering it is recommended that the Drypack instructions in the "Quality Reference Handbook" (order number 9398 510 63011) are followed. QUICK REFERENCE DATA SYMBOL VDD Itot fsys floop tjitter Notes 1. Digital clocks are silent and analog bias current is zero. 2. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock generation see Section "PLLs and clock generation". PARAMETER supply voltage total supply current system frequency loop bandwidth frequency short term stability time damping factor jitter during 1 line (64 s) note 1 note 2 CONDITIONS all positive supply pins tbf - 4 - - MIN. 4.5 TYP. 5.0 220 27 - - 0.7 MAX. 5.5 tbf 30 - 4 - V mA MHz kHz ns - UNIT
February 1995
3
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dbook, full pagewidth
February 1995
99 98 94 96 93 97 95 100 92 91 82 81 89 90 72 73 9 8 47 45 MY MU MV MAI bias MAV refT MAV refB CLAMP AND A/D CONVERTER ACQUISITION MAIN
BLOCK DIAGRAM
Philips Semiconductors
Picture-in-Picture (PIP) controller for NTSC
SV SSD MVSSD MAVSSD MAV SSA SAVSSD SAVSSA RAS WE SAVDDA SV DDD MV DDD MAVDDD MAV DDA SAV DDD CAS DT 44 32
SC DAO0 to 7 27 DAI0 to 7 AD0 to 8
DAV SSD
DAV SSA DAV DDA 20 21 18 14 16 19 13 15 17
DAV DDD 11 10
36,39,40,38 29,31,35,33 41,46,37,34 26,25,30,28
48 to 56
DY DU DV DAI bias DAV refTU DAV refTV DAV refTY
D/A CONVERTER AND BUFFER
SAB9075H
SY SU SV SAI bias SAV refT SAV refB 87 83 85 88 86 84
MEMORY CONTROL
4
CLAMP AND A/D CONVERTER
ACQUISITION SUB
DISPLAY
24
DBF
HUE SAT MMUTE SMUTE
70 69 67 68
65 66 HUE AND SAT D/A CONVERTERS DISPLAY TIMING CONTROL AND PLL BLOCK I C-BUS
2
SCL SDA POR A0
63 64 75
MBE084
22 I C VDD
2
42 V DDD
43 V SSS
71 SV sync
23
74
76
77
78
79
80
3
4
5
7
2
1
59
60
61 TM2
58
6
SPVDDD
SPI bias
MVsync
SPVSSD
MH sync MPV SSD MPV SSA TM0 SPVSSA SPVDDA SH sync TM1 MPI bias MPV DDD MPV DDA
MTCLK TC STCLK
Preliminary specification
SAB9075H
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
PINNING SYMBOL MPVDDA MPVSSA MHsync MPIbias MPVSSD MTCLK MPVDDD MVDDD MVSSD DAVDDD DAVSSD n.c. DAVrefTU DU DAVrefTV DV DAVrefTY DY DAIbias DAVSSA DAVDDA I2CVDD MVsync DBF DAI5 DAI4 SC DAI7 DAI0 DAI6 DAI1 DT DAI3 DAO7 DAI2 DAO0 DAO6 DAO3 DAO1 DAO2 February 1995 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I/O I/O I I I/O I I/O I/O I/O I/O I/O - I/O O I/O O I/O O I I/O I/O I/O I O I I O I I I I O I O I O O O O O TYPE E030 E009 E027 E027 E009 HPP01 E030 E030 E009 E030 E009 - E027 E027 E027 E027 E027 E027 E027 E009 E030 E030 HPP01 SPF20 HPP01 HPP01 OPF20 HPP01 HPP01 HPP01 HPP01 OPF20 HPP01 OPF20 HPP01 OPF20 OPF20 OPF20 OPF20 OPF20 5 DESCRIPTION
SAB9075H
analog positive power supply for PLL main-channel analog negative power supply for PLL main-channel horizontal synchronization for main-channel analog bias reference current for PLL main-channel digital negative power supply for PLL main-channel test clock for main-channel digital positive power supply for PLL main-channel digital positive power supply for main-channel core digital negative power supply for main-channel core digital positive power supply for DACs digital negative power supply for DACs not connected analog reference voltage for top U DAC analog U output analog reference voltage for top V DAC analog V output analog reference voltage for top Y DAC analog Y output analog bias reference current for DACs analog negative power supply for DACs analog positive power supply for DACs positive supply for HUE and SAT decoders vertical synchronization for main-channel fast blanking control output signal data bus input from memory; bit 5 data bus input from memory; bit 4 memory shift clock data bus input from memory; bit 7 data bus input from memory; bit 0 data bus input from memory; bit 6 data bus input from memory; bit 1 memory data transfer; active LOW data bus input from memory; bit 3 data bus output to memory; bit 7 data bus input from memory; bit 2 data bus output to memory; bit 0 data bus output to memory; bit 6 data bus output to memory; bit 3 data bus output to memory; bit 1 data bus output to memory; bit 2
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
SYMBOL DAO4 VDDD VSSS WE CAS DAO5 RAS AD0 AD8 AD1 AD6 AD2 AD5 AD3 AD4 AD7 n.c. TC TM0 TM1 TM2 n.c. POR A0 SCL SDA MMUTE SMUTE SAT HUE SVsync SVSSD SVDDD SPVDDD STCLK SPVSSD SPIbias SHsync SPVSSA SPVDDA SAVDDD February 1995
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
I/O O I/O I/O O O O O O O O O O O O O O - I I I I - I I I I/O O O O O I I/O I/O I/O I I/O I I I/O I/O I/O
TYPE OPF20 E030 E009 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 OPF20 - HPP01 HPP01 HPP01 HPP01 - HUP07 HPF01 HPF01 IOI41 SPF20 SPF20 E027 E027 HPP01 E009 E030 E030 HPP01 E009 E027 E027 E009 E030 E030 6
DESCRIPTION data bus output to memory; bit 4 digital positive power supply for peripherals digital negative power supply for peripherals memory write enable; active LOW memory column address strobe; active LOW data bus output to memory; bit 5 memory row address strobe; active LOW memory address bus; bit 0 memory address bus; bit 8 memory address bus; bit 1 memory address bus; bit 6 memory address bus; bit 2 memory address bus; bit 5 memory address bus; bit 3 memory address bus; bit 4 memory address bus; bit 7 not connected test control test mode 0 test mode 1 test mode 2 not connected power-on reset I2C-bus address 0 selection pin shift clock for I2C-bus shift I2C-bus input data; acknowledge I2C-bus output data mute output for main-channel mute output for sub-channel analog output for SAT decoder analog output for HUE decoder vertical synchronization for sub-channel digital negative power supply for sub-channel core digital positive power supply for sub-channel core digital positive power supply for PLL sub-channel test clock for sub-channel digital negative power supply for PLL sub-channel analog bias reference current for PLL sub-channel horizontal synchronization for sub-channel analog negative power supply for PLL sub-channel analog positive power supply for PLL sub-channel digital positive power supply for ADC sub-channel
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
SYMBOL SAVSSD SU SAVrefB SV SAVrefT SY SAIbias SAVSSA SAVDDA MAVDDA MAVSSA MAIbias MU MAVrefB MV MAVrefT MY MAVSSD MAVDDD Table 1
PIN 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
I/O I/O I I/O I I/O I I I/O I/O I/O I/O I I I/O I I/O I I/O I/O
TYPE E009 E027 E027 E027 E027 E027 E027 E009 E030 E030 E009 E027 E027 E027 E027 E027 E027 E009 E030
DESCRIPTION digital negative power supply for ADC sub-channel analog U input for sub-channel analog reference voltage for bottom ADC sub-channel analog V input for sub-channel analog reference voltage for top ADC sub-channel analog Y input for sub-channel analog bias reference current for ADC sub-channel analog negative power supply for ADC sub-channel analog positive power supply for ADC sub-channel analog positive power supply for ADC main-channel analog negative power supply for ADC main-channel analog bias reference current for ADC main-channel analog U input for main-channel analog reference voltage for bottom ADC main-channel analog V input for main-channel analog reference voltage for top ADC main-channel analog Y input for main-channel digital negative power supply for ADC main-channel digital positive power supply for ADC main-channel
Pin type explanation DESCRIPTION VDD pin; diode to VSS VSS pin; diode to VDD analog input pin; diode to VDD and VSS digital input pin; CMOS levels, diode to VSS digital input pin; CMOS levels, diode to VDD and VSS digital input pin; CMOS levels with hysteresis, pull up resistor to VDD, diode to VDD and VSS I2C-bus pull-down output stage; CMOS input levels digital output pin digital output pin; slew rate controlled
PIN TYPE E030 E009 E027 HPF01 HPP01 HUP07 IOI41 OPF20 SPF20
February 1995
7
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SAV DDD 81 SAV SSD 82 SU 83 SAVrefB 84 SV 85 SAV refT 86 SY 87 SAI bias 88 SAV SSA 89 SAV DDA 90 MAV DDA 91 MAV SSA 92 MAI bias 93 MU 94 MAVrefB 95 MV 96 MAV refT 97 MY 98 MAVSSD 99 MAVDDD 100 MV SSD 9 DAV DDD 10 DAV SSD 11 n.c. 12 DAV refTU 13 DU 14 DAV refTV 15 DV 16 DAV refTY 17 DY 18 DAI bias 19 DAVSSA 20 DAVDDA 21 I 2 C V DD 22 MV sync 23 DBF 24 DAI5 25 DAI4 26 SC 27 DAI7 28 DAI0 29 DAI6 30 1 2 3 4 5 6 7 8
Philips Semiconductors
Picture-in-Picture (PIP) controller for NTSC
74 SPVDDD 73 SVDDD 72 SVSSD
80 SPVDDA 79 SPVSSA 78 SH sync
77 SPI bias 76 SPVSSD
67 MMUTE
68 SMUTE
71 SV sync
75 STCLK
63 POR
70 HUE
66 SDA
61 TM2
60 TM1
59 TM0
69 SAT
65 SCL
56 AD7
55 AD4
54 AD3
53 AD5
52 AD2
51 AD6 50 AD1 49 AD8 48 AD0 47 RAS 46 DAO5 45 CAS 44 WE 43 V SSS 42 V DDD 41 DAO4 40 DAO2 39 DAO1 38 DAO3 37 DAO6 36 DAO0 35 DAI2 34 DAO7 33 DAI3 32 DT 31 DAI1
MBE083
62 n.c.
SAB9075H
MPV DDD
MPV DDA
MH sync MPI bias
MPVSSD
MPV SSA
MV DDD
MTCLK
57 n.c.
58 TC
64 A0
8
Preliminary specification
SAB9075H
Fig.2 Pin configuration.
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
FUNCTIONAL DESCRIPTION Acquisition area The acquisition area is in the centre of the visible screen area. Vertically 228 lines are sampled. Horizontally 672 Y-pixels are processed. The exact active processing area can be fine tuned in horizontal (2 pixels/steps, 16 steps) and vertical (1 line/step, 16 steps) direction for both main and sub-channel by the I2C-bus (see Fig.3). The given numbers are pixel numbers at a 13.5 MHz data rate. The signals, which are dependent on the I2C-bus registers, can also be related to the Hsync, in which event they are delayed by 68 pixels. Chrominance format The chrominance format is 4 : 1 : 1. The YUV signals are sampled at a rate of 27 MHz and then filtered and subsampled to a data rate of 13.5 MHz.
SAB9075H
It is expected that the input signals do not contain frequencies outside the video bandwidth (YBW = 4.5 MHz; UBW and VBW = 1.125 MHz). Display area The display area is shown in Fig.4. The given numbers are pixels at a data rate of 13.5 MHz. The signals are related to the burstkey and the Vsync. Dependent on the I2C-bus registers the signals can also be related to the Hsync. The internal 13.5 MHz data rate is upsampled to the double frequency (27 MHz) and then fed to the DACs. The display output can be fine positioned by the I2C-bus in 64 steps of 4 pixels in horizontal direction and 64 steps of 1 line/field in vertical direction.
handbook, full pagewidth
32
clamp 68 H sync burstkey 80 104 18 FT FT FT 1/1, 1/3 and 1/4 reduction 1/2 reduction 672 624 864
V sync
262.5
228
MBE085
18
FT
Fig.3 Acquisition area.
February 1995
9
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
handbook, full pagewidth
68
864
H sync burstkey 36 V sync 11 FT FT 672
262.5
228
MBE086
11
FT
Fig.4 Display area.
February 1995
10
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
PIP modes
SAB9075H
The controller contains two independent acquisition-channels which provide the scaling factors to support the range of different modes. With the external memory of 2 Mbit it is possible to select between single, double and multi-PIP modes. Table 2 gives an overview of the different PIP modes. Table 2 PIP modes SUB SIZE(1) MODE SUB MAIN PIXELS
1 1 1
MAIN SIZE(1) PIXELS - - 304P, 108L - 304P, 108L - 304P, 108L 216P, 72L - - REDUCTION(2) - -
1 2H, 1 1 1 2V
REDUCTION(2)
1 H, 4 1 H, 3 1 H, 2 1 H, 4 1 H, 4 1 H, 4 1 H, 4 1 H, 3 1 1 1 1 1 1 1 1
4 : 3 main + 4 : 3 sub to 4 : 3 screen or 16 : 9 main + 16 : 9 sub to 16 : 9 screen 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 SPS SPL DP MP3 MP4 MP7 MP8 MP9
16 9 4
- -
1 4
160P, 53L 216P, 72L 304P, 108L 160P, 53L
4
4V 3V 2V 4V 4V 4V 4V 3V
3 x 116 3 x 116 7x 7x
1 1 16 16
-
1
-
1 2H, 2V
160P, 53L 160P, 53L 160P, 53L 216P, 72L
-
1 1 4 9
-
1 1 2H, 2V 1 3H, 3V
8 x 19
1 1
16 : 9 sub + 4 : 3 main to 4 : 3 screen 2.1 2.2 SPS SPL
16 9
- - -
1 4
216P, 53L 304P, 72L
1 H, 1 V 3 4 1 H, 1 V 2 3
- -
4 : 3 sub + 16 : 9 main to 16 : 9 screen 3.1 3.2 Notes 1. The given sub/main sizes are visible PIP sizes, a border is drawn around these PIPs and does not influence these sizes. The size of the border is 4 pixels wide and 2 lines/fields high. 2. The SAB9075H can be set in automatic mode in which the reduction factors are automatically set by the mode select and aspect ratio select bits of the I2C-bus. If the automatic mode is switched OFF the reduction factors can be set manually. This will give more flexibility to adjust the aspect ratios of incoming signals. PIP positions The positions are graphically depicted in Figs 5 to 17. SPS DP
1 1 16 4
160P, 72L 216P, 108L
1 H, 1 V 4 3 1 H, 1 V 3 2
304P, 108L
1
2H,
1
2V
February 1995
11
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
burstkey handbook, full pagewidth V sync 36 FT 672 11 11 57 FT 24 168 288 168 24
S
92
228
57 11
MBE087
Fig.5 Single-PIP, size 116 (mode SPS).
burstkey handbook, full pagewidth V sync 36 FT 672 11 11 FT 24 224 176 224 24
76
S
54
228
76
11
MBE088
Fig.6 Single-PIP, size 19 (mode SPL). February 1995 12
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 24 312 312 24
58
112
S
M
228
58
MBE089
Fig.7 Double-PIP, size 116 (mode DP).
burstkey handbook, full pagewidth V sync 36 FT 672 11 24 57 5 57 5 57 23
MBE090
FT
36
168
264
168
36
C0
C1
228
C2
Fig.8 Multi PIP, 3 x sub 116 (mode MP3). February 1995 13
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 24 57 5 57 5 57 35 23
MBE091
36
168
120
312
36
34
C0
112
C1
M
228
C2
Fig.9 Multi-PIP, 3 x sub 116, 1 x main 14 (mode MP4).
burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 24 57 5 57 5 57 35 23
MBE092
36
312
120
168
36
34
C0
112
M
C1
228
C2
Fig.10 Multi-PIP, 3 x sub 116, 1 x main 14 (mode MP4, Right). February 1995 14
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 168 168 168 168
57
C0
57
C1
228
57
C2
57
C3
C4
C5
C6
MBE093
Fig.11 Multi-PIP, 7 x sub 116, main life (mode MP7).
burstkey handbook, full pagewidth V sync 36 FT 672 168 11 FT 96 168 168 312 168 96 30 57
C0
57
C1
M
112 228
57
C2
29
57
C3
C4
C5
C6
MBE094
Fig.12 Multi-PIP, 7 x sub 116, 1 x main 14 (mode MP8). February 1995 15
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
burstkey handbook, full pagewidth V sync 36 FT 672 11 FT 224 224 224
76
C0
C1
C2
76
C3
M
C4
228
76
C5
C6
C7
MBE095
Fig.13 Multi-PIP, 8 x sub 19, 1 x main 19 (mode MP9).
burstkey handbook, full pagewidth V sync 36 FT 672 11 11 FT 24 168 288 168 24
76
S
54
228
76
11
MBE097
Fig.14 Single-PIP, 4 : 3 sub to 16 : 9 screen (mode SPS).
February 1995
16
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
burstkey handbook, full pagewidth V sync 36 FT 672 11 11 57 FT 24 224 176 224 24
S
92
228
57 11
MBE096
Fig.15 Single-PIP, 16 : 9 sub to 4 : 3 screen (mode SPS).
burstkey handbook, full pagewidth V sync 36 FT 672 11 11 FT 24 312 312 24
76
S
54
228
76
11
MBE098
Fig.16 Single-PIP, 16 : 9 sub to 4 : 3 screen (mode SPL).
February 1995
17
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
burstkey handbook, full pagewidth V sync 36 FT 696 11 FT
238
MBE099
Fig.17 Factory mode.
February 1995
18
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
I2C-bus The I2C-bus provides bi-directional 2-line communication between different ICs. The SDA line is the Serial Data line and the SCL serves as Serial Clock Line. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. The SAB9075H has the I2C-bus addresses 2C and 2E, switchable by the pin A0. Valid subaddresses are 00H to 0FH. Table 3 Overview of I2C-bus addresses (note 1) Data Bytes SA 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Notes BIT 7 PIPON HPOS note 2 note 2 MREDH1 note 2 note 2 note 2 note 2 BIT 6 MANRED VPOS note 2 note 2 MREDH0 CBSEL2 MBON SBON CBON BIT 5 MFREEZE DHFP5 DVFP5 MREDV1 CBSEL1 MBBRT1 SBBRT1 CBBRT1 BGBRT1 MHSYNC MAAHFP3 SAAHFP3 HUE5 SAT5 note 2 BIT 4 SFREEZE DHFP4 DVFP4 MREDV0 CBSEL0 MBBRT0 SBBRT0 CBBRT0 BGBRT0 MFPOL MAAHFP3 SAAHFP3 HUE4 SAT4 note 2 BIT 3 MODE3 note 2 DHFP3 DVFP3 SREDH1 note 2 note 2 note 2 note 2 note 2 SCOLPOL MAAVFP3 SAAVFP3 HUE3 SAT3 note 2 BIT 2 MODE2 BCOLPOL DHFP2 DVFP2 SREDH0 SLSEL2 MBCOL2 SBCOL2 CBCOL2 BGCOL2 SVSPOL MAAVFP3 SAAVFP3 HUE2 SAT2 note 2
SAB9075H
I2C-bus control is in accordance with the I2C-bus protocol. First a start sequence must be put on the I2C-bus, then the I2C-bus address 2C or 2E, followed by a subaddress 00 to 0F. After this sequence, the data of the subaddress must be sent. An auto-increment function then gives the option `send data' of the incremented subaddresses until a stop sequence has been given.
BIT 1 MODE1 MVFILT DHFP1 DVFP1 SREDV1 SLSEL1 MBCOL1 SBCOL1 CBCOL1 BGCOL1 SHSYNC MAAVFP3 SAAVFP3 HUE1 SAT1 note 2
BIT 0 MODE0 SVFILT DHFP0 DVFP0 SREDV0 SLSEL0 MBCOL0 SBCOL0 CBCOL0 BGCOL0 SFPOL MAAVFP3 SAAVFP3 HUE0 SAT0 note 2
MASPECT SASPECT
FACMODE BGON MCOLPOL MVSPOL MAAHFP3 SAAHFP3 note 2 note 2 MMUTE MAAHFP3 SAAHFP3 note 2 note 2 SMUTE
1. Table 3 gives an overview of the I2C-bus addresses. They will be explained in more detail in the following pages. 2. Some address spaces are unused but already implemented for future functionality.
February 1995
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
Table 4 PIP mode control (note 1) PIP MODE NAME SPS SPS SPS SPS SPL SPL SPL DP DP DP MP3 MP4 MP7 MP8 MP9 Notes 1. Table 4 gives an overview of the possible PIP modes and how to set them via the I2C-bus. 2. The columns main and sub-reduction indicate how the PIP pictures appear on the screen. 3. The column mode corresponds to the lower 4 bits of I2C-bus Register 0. 4. The main and sub-aspect ratios correspond to the bits 5 and 6 of I2C-bus Register 0. MODE(3) 0000 0000 0000 0000 0001 0001 0001 1010 1010 1010 0110 1110 0100 1100 1001 ASPECT RATIO MAIN(4) 0 0 1 1 0 0 1 0 1 1 X X X X X SUB(4) 0 1 0 1 0 1 X X 0 1 X X X X X MAIN-REDUCTION(2) HOR - - - - - - -
1 2 1 2 1 2
SAB9075H
SUB-REDUCTION(2) HOR
1 4 1 3 1 4 1 4 1 3 1 2 1 3 1 2 1 3 1 2 1 4 1 4 1 4 1 4 1 3
VER - - - - - - -
1 2 1 2 1 2
VER
1 4 1 4 1 3 1 4 1 3 1 3 1 3 1 2 1 2 1 2 1 4 1 4 1 4 1 4 1 3
-
1 2
-
1 2
-
1 2 1 3
-
1 2 1 3
February 1995
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
Table 5 BIT 7 6 5 4 3 2 1 0 Notes Register 0; PIP mode control register MODE PIPON MANRED MASPECT(4) SASPECT(4) MODE(3)(5) MODE(2)(5) MODE(1)(5) MODE(0)(5) RESULT logic 0 = PIP function is OFF(1); logic 1 = PIP function is ON
SAB9075H
logic 0 = automatic reduction factors(2); logic 1 = manual reduction factors(3) main-aspect ratio; 0 = 4 : 3; 1 = 16 : 9 sub-aspect ratio; 0 = 4 : 3; 1 = 16 : 9 PIP mode PIP mode PIP mode PIP mode
1. With PIPON in OFF mode the fast blanking signal is made inactive. All other functions will operate as if the circuit were in operational mode. 2. With MANRED set to logic 0 the reduction factors will be set automatically, dependent on the PIP mode and the aspect ratio bits of main and sub (bits 5 and 4). Table 4 indicates which bits should be set to obtain a certain PIP mode. 3. With MANRED set to logic 1 the calculation of the reduction factors is not carried out and should be set by Register 4 (see Table 9). Only combinations with MANRED set to logic 0 are guaranteed. 4. MASPECT and SASPECT are used in automatic mode (MANRED) to indicate the type of input signals, together with MODE the PIP mode can be set (see Table 4). In manual mode these bits are ignored. 5. The MODE bits set the PIP mode. For the multi-PIP modes the frozen PIPs are set to the 30% grey colour. Once a PIP has been made live it will always display the last video data. Table 6 BIT 7 6 5 4 3 2 1 0 Notes 1. HPOS and VPOS determine the general location of the sub-PIP on the screen. HPOS only operates in modes SPS, SPL, DP, MP3 and MP4. VPOS only operates in modes SPS and SPL. The default location of the sub-pictures will be left top. 2. MFREEZE will freeze the main-picture, and SFREEZE will freeze the sub-picture selected by the live select bits as in Register 8 (see Table 13). 3. BCOLPOL can invert the border polarity of U and V. 4. MVFILT and SVFILT set the type of vertical filtering for the main and sub-channel. Mode 1 means that diagonal lines are linearized, in Mode 0 this option is switched OFF. This filtering mode only operates with vertical reduction factors 13 and 14. February 1995 21 Register 1; general control register MODE HPOS(1) VPOS(1) MFREEZE(2) SFREEZE(2) - BCOLPOL(3) MVFILT(4) SVFILT(4) logic 0 = left; logic 1 = right logic 0 = top; logic 1 = bottom logic 0 = main-freeze is OFF; logic 1 = main-freeze is ON logic 0 = sub-freeze is OFF; logic 1 = sub-freeze is ON not used border UV polarity; logic 0 = +(B-Y), +(R-Y); logic 1 = -(B-Y), -(R-Y) main-vertical filter mode; logic 0 = Mode 0; logic 1 = Mode 1 sub-vertical filter mode; logic 0 = Mode 0; logic 1 = Mode 1 RESULT
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
Table 7 BIT 7 6 5 4 3 2 1 0 Note - - DHFP(5) DHFP(4) DHFP(3) DHFP(2) DHFP(1) DHFP(0) Register 2; display horizontal fine position register MODE not used not used horizontal fine position (64 steps) horizontal fine position horizontal fine position horizontal fine position horizontal fine position horizontal fine position DESCRIPTION(1)
SAB9075H
1. The display position can be set in steps of 4 pixels/lines and 1 line/field. The offsets on the display position are depicted in Fig.4. Table 8 BIT 7 6 5 4 3 2 1 0 Note 1. The display position can be set in steps of 4 pixels/lines and 1 line/field. The offsets on the display position are depicted in Fig.4. Table 9 BIT 7 6 5 4 3 2 1 0 Note 1. 01 = 11; 10 = 12; 11 = 13; 00 = 14. Register 4; reduction factor register MODE MREDH(1) MREDH(0) MREDV(1) MREDV(0) SREDH(1) SREDH(2) SREDV(1) SREDV(0) main-horizontal reduction factor main-horizontal reduction factor main-vertical reduction factor main-vertical reduction factor sub-horizontal reduction factor sub-horizontal reduction factor sub-vertical reduction factor sub-vertical reduction factor DESCRIPTION(1) - - DVFP(5) DVFP(4) DVFP(3) DVFP(2) DVFP(1) DVFP(0) Register 3; display vertical fine position register MODE not used not used vertical fine position (64 steps) vertical fine position vertical fine position vertical fine position vertical fine position vertical fine position DESCRIPTION(1)
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
Table 10 Register 5; channel select register BIT 7 6 5 4 3 2 1 0 Notes - CBSEL(2)(1) CBSEL(1)(1) CBSEL(0)(1) - SLSEL(2)(2) SLSEL(1)(2) SLSEL(0)(2) MODE not used channel-border select (maximum 8 channels) channel-border select channel-border select not used sub-live select (maximum 8 channels) sub-live select sub-live select DESCRIPTION
SAB9075H
1. With CBSEL one border of the displayed sub-borders can be selected independently of the SLSEL. This only operates when the channel select-border is ON as in Register 8 (see Table 13) and when the selected channel number is displayed. 2. With SLSEL the active sub-live picture can be selected. This only operates when the SFREEZE is OFF as in Register 1 (see Table 6) and when the selected channel is displayed. Background and main, sub and channel-border colour and brightness handling Registers 6 to 9 (see Tables 11 to 14) handle background and main, sub and channel-border colour and brightness. The borders and background can be set ON and OFF. Table 11 Register 6; main-border control register BIT 7 6 5 4 3 2 1 0 - MB0N MBBRT(1) MBBRT(0) - MBCOL(2) MBCOL(1) MBCOL(0) MODE not used logic 0 = MB is OFF; logic 1 =MB is ON main-border brightness (4 steps) main-border brightness not used main-border colour (8 colours) main-border colour main-border colour DESCRIPTION Background, main and sub-borders are black when they are OFF. The channel-border gets the current sub-border colour when it is switched OFF. The brightness can be set in 4 steps (30%, 50%, 70% and 100%). Eight different colours can be set in accordance with Table 15.
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
Table 12 Register 7; sub-border control register BIT 7 6 5 4 3 2 1 0 - SBON SBBRT(1) SBBRT(0) - SBCOL(2) SBCOL(1) SBCOL(0) MODE not used logic 0 = SB is OFF; logic 1 = SB is ON sub-border brightness (4 steps) sub-border brightness not used sub-border colour (8 colours) sub-border colour sub-border colour DESCRIPTION
SAB9075H
Table 13 Register 8; channel-border control register BIT 7 6 5 4 3 2 1 0 - CBON CBBRT(1) CBBRT(0) - CBCOL(2) CBCOL(1) CBCOL(0) MODE not used logic 0 = CB is OFF; logic 1 = CB is ON channel-border brightness (4 steps) channel-border brightness not used channel-border colour (8 colours) channel-border colour channel-border colour DESCRIPTION
Table 14 Register 9; background control register BIT 7 6 5 4 3 2 1 0 Note 1. The FACMODE bit controls the factory mode which shows an enlarged background colour as depicted in Fig.17 (BGON must be set). MODE FACMODE(1) BGON BGBRT(1) BGBRT(0) - BGCOL(2) BGCOL(1) BGCOL(0) DESCRIPTION logic 0 = FM is OFF; logic 1 = FM is ON logic 0 = BG is OFF; logic 1 = BG is ON background brightness (4 steps) background brightness not used background colour (8 colours) background colour background colour
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
Table 15 Colour table BRIGHTNESS (%)(1) COLOUR TYPE 0 Black/white Blue Red Magenta Green Cyan Yellow Note 40H - - - - - - 10 50H - - - - - - 30 60H 41H 42H 43H 44H 45H 46H 50 70H 51H 52H 53H 54H 55H 56H 60 47H - - - - - - 70 57H 61H 62H 63H 64H 65H 66H
SAB9075H
80 67H - - - - - -
100 77H 71H 72H 73H 74H 75H 76H
1. The values in are the I2C-bus register values for the Colour Control Registers 6 to 9 (see Tables 11 to 14). The values are hexadecimal values of which the left part indicates the brightness and the right part the colour value. Table 16 Border display PIP MODES MP4 MP8 MP9 FFS SPS SPL MBON OFF OFF ON ON - - OFF DP OFF ON ON MP3 MP4 MP7 MP8 MP9 Notes 1. The BGON I2C-bus bit controls the display area outside the PIP and border area, set to ON means that the background gets the BGCOL colour value. 2. The main and sub-border displays are dependent on the I2C-bus switches. 3. `Live BG' means that the original picture is shown. - - - - BGON(1) OFF ON OFF ON - - OFF ON OFF ON OFF ON OFF ON SBON - - - - OFF ON OFF OFF ON ON OFF OFF ON ON CBON - - - - - - - - - - ON ON ON ON live MAINBORDER DISPLAY(2) live BG(3) BGCOL MBCOL MBCOL - - BG(3) live BGCOL MBCOL MBCOL - - - - BACKGROUND DISPLAY live BG(3) BGCOL live BG(3) - - BG(3) BGCOL live BG(3) BGCOL live BG(3) BGCOL live BG(3) BGCOL BGCOL SUBCHANNEL BORDER BORDER DISPLAY(2) DISPLAY - - - - live BG(3) SBCOL live BG(3) BGCOL SBCOL SBCOL live BG(3) BGCOL SBCOL SBCOL - - - - - - - - - - CBCOL CBCOL CBCOL CBCOL
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
Table 17 Register A; decoder format register BIT 7 6 5 4 3 2 1 0 Notes 1. MCOLPOL and SCOPOL invert the UV video data. MODE MCOLPOL(1) MVSPOL(2) MHSYNC(3) MFPOL SCOLPOL(1) SVSPOL(2) SHSYNC(3) SFPOL RESULT main-UV polarity; logic 0 = original; logic 1 = inverted
SAB9075H
main-vertical sync polarity; logic 0 = positive pulse; logic 1 = negative pulse main-horizontal sync selection; logic 0 = burst edge; logic 1 = H - sync main-field polarity; inverts field identification window sub-UV polarity; logic 0 = original; logic 1 = inverted sub-vertical sync polarity; logic 0 = positive pulse; logic 1 = negative pulse sub-horizontal sync selection; logic 0 = burst edge; logic 1 = H - sync sub-field polarity, inverts field identification window
2. MVSPOL and SVSPOL determine the active edge of the Vsync. If VSPOL is logic 0, the positive edge of the Vsync will be taken; if VSPOL is logic 1, the negative edge of the Vsync will be taken. 3. MHSYNC and SHSYNC determine whether the Hsync signal or the burstkey is used as internal horizontal synchronization. The exact timing of the Vsync in relation to the Hsync reference pulse is depicted in Fig.18. A field identification window determines whether a Vsync is being handled as a 1st field or a 2nd field. This field identification window can be inverted by the FPOL bit. If FPOL is logic 0 and an active edge of the Vsync occurs when the F-ID signal is logic 0, it will be regarded as the 1st field. If FPOL is logic 0 and an active edge of the Vsync occurs when the F-ID signal is logic 1, it will be regarded as the 2nd field. If FPOL is logic 1 the 1st and 2nd field IDs are changed over.
handbook, full pagewidth H (external)
sync
field ID (internal) (number of pixels) 43 V sync (external) 1st field V sync (external)
MBE100
389
432
2nd field
Fig.18 Vsync timing and field identification.
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
Table 18 Register B; main-acquisition area fine position BIT 7 6 5 4 3 2 1 0 Notes MODE MAAHFP(3) MAAHFP(2) MAAHFP(1) MAAHFP(0) MAAVFP(3)(2) MAAVFP(2)(2) MAAVFP(1)(2) MAAVFP(0)(2) DESCRIPTION(1) main-acquisition area horizontal fine position main-acquisition area horizontal fine position main-acquisition area horizontal fine position main-acquisition area horizontal fine position main-acquisition area vertical fine position main-acquisition area vertical fine position main-acquisition area vertical fine position main-acquisition area vertical fine position
SAB9075H
1. The acquisition area can be adjusted in 16 steps of 2 pixels horizontally and 1 line/field vertically. 2. With MAAVFP a complete field must have been processed before the next Vsync occurs. This is relevant for non-standard signals. Table 19 Register C; sub-acquisition area fine position BIT 7 6 5 4 3 2 1 0 Notes 1. The acquisition area can be adjusted in 16 steps of 2 pixels horizontally and 1 line/field vertically. 2. With SAAVFP a complete field must have been processed before the next Vsync occurs. This is relevant for non-standard signals. MODE SAAHFP(3) SAAHFP(2) SAAHFP(1) SAAHFP(0) SAAVFP(3)(2) SAAVFP(2)(2) SAAVFP(1)(2) SAAVFP(0)(2) DESCRIPTION (1) sub-acquisition area horizontal fine position sub-acquisition area horizontal fine position sub-acquisition area horizontal fine position sub-acquisition area horizontal fine position sub-acquisition area vertical fine position sub-acquisition area vertical fine position sub-acquisition area vertical fine position sub-acquisition area vertical fine position
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
Auxiliary registers
SAB9075H
The Auxiliary Registers D to F (see Tables 20 to 22) are implemented to generate I2C-bus controlled signals for circuits which do not have an on-board I2C-bus. Table 20 Register D; Auxiliary Control Register 1 BIT 7 6 5 4 3 2 1 0 - - HUE(5) HUE(4) HUE(3) HUE(2) HUE(1) HUE(0) MODE not used not used hue control (output pin HUE) hue control hue control hue control hue control hue control DESCRIPTION
Table 21 Register E; Auxiliary Control Register 2 BIT 7 6 5 4 3 2 1 0 - - SAT(5) SAT(4) SAT(3) SAT(2) SAT(1) SAT(0) MODE not used not used saturation control (output pin SAT) saturation control saturation control saturation control saturation control saturation control DESCRIPTION
Table 22 Register F; Auxiliary Control Register 3 BIT 7 6 5 4 3 2 1 0 MODE MMUTE SMUTE - - - - - - DESCRIPTION data bit directly to output pin MMUTE data bit directly to output pin SMUTE not used not used not used not used not used not used
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
External memory For the external memory two VDRAMS of type Mitsubishi M5442256 are used. They have a storage capacity of 262144 words of 4-bit each and will be used in parallel. An overview of the timing to the VDRAM is depicted in Fig.19. Three different timing modes are shown. If the SAB9075 is not in one of these three modes, it is in idle mode in which all the control signals are HIGH. An idle mode takes at least 4 clock periods. Switching from one mode to another is always carried out via this idle mode. The clock signal shown is an internal clock derived from the PLLs and is approximately 27 MHz. Main and sub-ADCs Both main and sub-channels convert the analog input signals to digital signals by three ADCs for each channel. The input levels of the ADCs are equal and can set by the MAVrefT, SAVrefT, MAVrefB, and SAVrefB pins.The reference levels are made internally by a resistor network which divides the analog VDD to a default set of preferred signal levels of 1.5 V. If the application requires a different set of levels the internal resistors can be shunted. External capacitors are required to filter AC components on the reference levels. The resolution of the ADCs is 6-bit and the sampling is carried out at the system frequency of 27 MHz. The bias current Ibias is made internally but can be increased or decreased. The inputs should be AC-coupled and an internal clamping circuit will clamp the input to MAVrefB and SAVrefB for the luminance channels and to MAV refT + MAV refB LSB ---------------------------------------------------- + ----------2 2 SAV refT + SAV refB LSB -------------------------------------------------- + ----------2 2 for the chrominance channels. The clamping starts at the active edge of the burstkey. For more information see chapter "Test and application information". Output DACs
SAB9075H
The digital processed signals are converted to analog signals by means of three DACs. The output voltages of these DACs are default set by the DAVrefTU, DAVrefTV and DAVrefTY pins for the TOP-levels. Default signal levels are 1.5 V. The output buffer after each DAC is a PMOS source follower. For more information see chapter "Test and application information". HUE and SAT DACs The HUE and SAT DACs are resistor DACs based on a R2R network. They have a direct control from their I2C-bus register and therefore their sample frequency is limited by the I2C-bus frequency. The output voltage is linear with the I2CVDD. Therefore the VDD of this block is a separate pin. PLLs and clock generation The SAB9075H has two PLLs on-board, one for the subchannel and one for the main-channel and the display part. The PLLs lock to the input signals MHsync and SHsync. The internal clock frequency is 1 728 times higher which is approximately 27 MHz in a standard NTSC system. The positive edges of the Hsync signals are the driving timing points. For good short term stability they have to be noise/jitter free.
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
handbook, full pagewidth CLOCK
RAS
CAS refresh cycle
CLOCK
RAS
CAS
AD0 to AD8
ROW
COLUMN
COLUMN
COLUMN
COLUMN
COLUMN
WE
DAI0 to DAI7 write cycle (SUB or MAIN)
CLOCK
RAS
CAS
AD0 to AD8
ROW
COLUMN
WE
DT read cycle
SC
DAO0 to DAO7
MBE101
SC cycles
Fig.19 VDRAM timing.
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDD VDD Tstg Tamb Vesd Ptot supply voltage supply voltage variation storage temperature operating ambient temperature electrostatic discharge handling total power dissipation PARAMETER - -25 0 - - MIN. -0.5 0.2 +150 70 - 1.5
SAB9075H
MAX. +6.5 V V C C V W
UNIT
THERMAL CHARACTERISTICS SYMBOL Rthj-a PARAMETER thermal resistance from junction to ambient in free air VALUE 38 UNIT K/W
QUALITY SPECIFICATION In accordance with SNW-FQ-611, Part E, dated 14 December 1992.
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
CHARACTERISTICS VDD = 5.0 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDD VSS VDD VSS IDDQ MPIVDDA SPIVDDA MAIVDDA SAIVDDA DIVDDA I2CVDD Itot AVrefT AVrefB Rinref VI Vi Ri RiY RiV RiU Ci Res fs DNL INL Vos cs PSRR positive supply voltage negative supply voltage maximum voltage difference between all positive supply pins maximum voltage difference between all negative supply pins quiescent current digital positive supply pins supply current PLL main supply current PLL sub supply current 3 main-ADCs supply current 3 sub-ADCs supply current 3 display DACs supply current HUE and SAT DACs total supply current note 2 note 1 4.5 - - - - - - - - - - tbf 5.0 0 0 0 2 2.5 2.5 36 36 18 2.5 220 PARAMETER CONDITIONS MIN. TYP.
SAB9075H
MAX.
UNIT
5.5 - 100 100 tbf tbf tbf tbf tbf tbf 5 tbf
V V mV mV A mA mA mA mA mA mA mA
Converter and clamping top reference voltage bottom reference voltage input resistance VrefT to VrefB DC input voltage AC input voltage (peak-to-peak value) input resistance input resistance for Y channel input resistance for V channel input resistance for U channel input capacitance resolution sample frequency rate differential non-linearity integral non-linearity input offset voltage channel separation power supply rejection ratio within channel to other channel note 4 clamping OFF clamping ON clamping ON clamping ON note 3 note 3 note 3; 1 ADC 1.0 0 tbf VrefB 1.0 1 - - - - - - -1.0 -1.0 -1.0 tbf tbf tbf 1.9 0.4 860 - 1.5 - 200 800 800 15 6 27 - - - 40 40 40 2.0 1.0 tbf VrefT - - - - - - - - +1.0 +1.0 +1.0 - - - V V V V M pF bit MHz LSB LSB LSB dB dB dB
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
SYMBOL TDclamp Tclamp VclampY VclampU VclampV VrefT Rinref Vo(max) RL(min) CL(max) Res fs DNL INL cs PSRR
PARAMETER delay burstkey edge to clamping start duration of clamping clamping voltage level Y clamping voltage level U clamping voltage level V
CONDITIONS - - ADout = 0H ADout = 20H ADout = 20H note 3 note 3; 1 DAC - - -
MIN. 0
TYP. - - - 2.33 Vs
MAX.
UNIT s s V V V
0.5 VT+B - 0.5 VT+B - 1.5 1.0 - - 50 7 27 - - 40 40 - - 50 6 - - 0 - - 1.0 15734 2.0 tbf VrefT - - - - +0.5 +1.0 - -
Digital-to-analog converter top reference voltage (Y, U and V) input resistance VrefT to VrefB maximum output voltage minimum load resistance maximum load capacitance resolution sample frequency rate differential non-linearity integral non-linearity channel separation power supply rejection ratio note 4 1.0 tbf VrefB 10 - - - -0.5 -1.0 tbf tbf V k V k pF bit MHz LSB LSB dB dB
Digital-to-analog converter HUE/SAT Vo RL(min) CL(max) Res DNL INL PSRR output voltage minimum load resistance maximum load capacitance resolution differential non-linearity integral non-linearity power supply rejection ratio note 2 note 2 VSS 100 - - -1.0 -1.0 - VDD - - - +1.0 +1.0 - V k pF bit LSB LSB dB
PLL and clock generation; note 4 VTOP VLOW Vslice fPLL Notes 1. Digital clocks are silent and analog bias current is zero. 2. The HUE and SAT DACs are based on a R2R ladder network as describe in the section "HUE and SAT DACs". The maximum output sample frequency is determined by the I2C-bus. 3. The input configuration of the ADCs is depicted in Fig.20. The minimum difference AVrefT - AVrefB should be larger than 1.0 V. The reference voltages can be calculated as follows: 1.9 0.4 V refT = AV DD x ------- V ; V refB = AV DD x ------- V 5.0 5.0 4. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock generation see section "PLLs and clock generation". February 1995 33 TOP-level input voltage LOW-level input voltage slicing voltage level below TOP input frequency 2.5 - 0.45 14750 PVDD 0.5 2.0 17250 V V V Hz
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
DC CHARACTERISTICS FOR DIGITAL PART All VDD pins = 4.5 to 5.5 V; Tamb = -20 to +75 C; unless otherwise specified. SYMBOL VIH PARAMETER HIGH level input voltage HPF01 HPP01 HUP07 VIL LOW level input voltage IOI41 HPF01 HPP01 HUP07 IOI41 Vhys VOH VOL hysteresis voltage HIGH level output voltage LOW level output voltage HUP07 OPF20; IOL = -2 mA; VDD = 4.5 V SPF20; IOL = -2 mA; VDD = 4.5 V IOI41; IOL = +2 mA; VDD = 4.5 V OPF20; IOL = +2 mA; VDD = 4.5 V SPF20; IOL = +2 mA; VDD = 4.5 V ILI ILOZ Rpu input leakage current three-state output leakage current internal pull up resistor HPF01 HPP01 IOI41; VDD = 5.5 V HUP07 CONDITIONS MIN. 70 70 80 70 - - - - - 4.4 4.4 - - - - - - 17 - - - - - - - - 33 - - - - - 0.1 0.1 0.2 - TYP.
SAB9075H
MAX. - - - - 30 30 20 30 - - - 0.15 0.15 0.15 1 1 5.0 134
UNIT %VDD %VDD %VDD %VDD %VDD %VDD %VDD %VDD %VDD V V V V V A A A k
AC CHARACTERISTICS FOR DIGITAL PART VDD = 4.5 5.5 V; Tamb = -20 to +75 C; unless otherwise specified. SYMBOL fsys tr tf Note 1. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock generation see section "PLLs and clock generation". PARAMETER system frequency rise time fall time note 1 VDD = 4.5 V VDD = 4.5 V CONDITIONS - - - MIN. 6 6 TYP. 27 MAX. 30 25 25 UNIT MHz ns ns
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
TEST AND APPLICATION INFORMATION Fig.20 shows how the ADCs and the DACs can be connected in the application. The generation of the reference voltages is carried out internally and they have to be externally decoupled for AC signals. For all ADCs and DACs the internal resistor division is such that a maximum signal voltage level of 1.5 V is obtained. For the ADCs there is a DC offset voltage of 0.4 V.
SAB9075H
A modification of these reference voltages can be achieved by external shunting. The ADC reference voltages are the same for all Y/U/V channels which means that their input levels need to be the same. The DAC voltage references can be set separately for Y/U/V channels. These reference voltages can be modified by shunting. The output buffers of the DACS are PMOS source followers with a minimum output load of 10 k.
handbook, full pagewidth
MAV DDA MAV refT MY
R top
3R top
DAVDDA
ADC
DAV refTY DAVrefTU
MU
ADC
DAV refTV
MV MAV refB MAV SSA SAV DDA SAV refT SY
ADC DAC R bottom R top VIDEO SIGNAL PROCESSING
DY
DU DAC DV DAC
ADC DAV SSA
SU
ADC
SV SAV refB SAV SSA
ADC
R bottom
MGC001
Fig.20 Analog application diagram ADCs and DACs.
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
handbook, full pagewidth
TMS44C250
TMS44C250
9 5V
4
4
4
4 5V 5V
0 V or 5 V SCL SDA CAS
DAO4 to DAO7
DAO0 to DAO3
AD0 to AD8
RAS
TM1
DAI4 to DAI7
TM0
TM2
SC
TC
V DDD
DAI0 to DAI3
MTCLK
V SSS
STCLK
MVDDD MVSSD
SVDDD SVSSD
POR
WE
DT
A0
SCL
MPI bias 5V 5V MPVDDA MPVSSA MPVDDD MPVSSD SPIbias 5V 5V 5V SPV DDA SPV SSA SPV DDD SPV SSD SAVDDD SAVSSD
SDA DAI bias DAVDDA DAVSSA DAVrefTY DAVrefTU DAVrefTV DBF DY DU DV DAVDDD DAVSSD MAVDDD MAVSSD MAI bias fast blanking control output analog Y output analog U output analog V output 5V 5V
5V
SAB9075H
I2 CVDD
MAVSSA MAVDDA 5V
SAIbias SAVDDA
SAVSSA SAVrefT
MAVrefB MAVrefT
SAVrefB SVsync
MH sync
MV sync
MMUTE MY
SH sync
SMUTE
HUE
SAT
MU
MV
SY SU SV
MGC053
5V main-channel mute output
5V
SAT HUE
sub-channel mute output U
U
VOUT
HUE
HOUT
HOUT
SAT
TDA8315T
CVBS/Y
TDA8315T
CVBS/Y
CVBS/Y sub-channel input
CVBS/Y main-channel input
Fig.21 Application diagram.
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VOUT
Y
Y
V
V
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAB9075H
SOT317-2
c
y X
80 81
51 50 ZE
A
e E HE A A2 A1 (A 3) Lp bp 100 1 wM D HD ZD B vM B 30 vMA 31 detail X L
wM pin 1 index
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.40 0.25 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.15 y 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
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Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SOLDERING Plastic quad flat-packs BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be
SAB9075H
applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
February 1995
38
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
NOTES
SAB9075H
February 1995
39
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729 India: Philips INDIA Ltd, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (081)730-5000, Fax. (081)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD36 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
533061/1500/01/pp40 Document order number: Date of release: February 1995 9397 745 30011
Philips Semiconductors

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